They asked about the design verification process, UVM concepts and coverage.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
the fundamental knowledge of uvm and the implementation
Tell about yourself, About Post graduation project
They mainly focused upon my resume and asked questions on projects
How would you verify a RAM memory with a single port read/write?
Verification methodology, computer architecture, data structures and algorithms, digital logic, Verilog
Write an assertion for AXI valid, ready.
How does branch prediction work? What hardware mechanisms alleviate mis-predicts?
Draw the inverter's voltage transfer curve and explain what happens in each phase. Draw the cross section of a transistor and explain body effect.
Resume projects are thoroughly asked
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