design an adder with a clock
Verification Interview Questions
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polymorphism in system verilog and virtaul interfaces.
Design a bitstream pattern detection finite state machine in the HDL of your choice.
about how to build an adder
One medium question on leetcode. Absolute software engineer question.
FiFo depth, Assertions, FSM, Clocks
described in the interview process.
Write a Scoreboard for verifying the average of 5 previous values, where the data is coming sequentially, I.e 1 value at every posedge of clk.
UVM questions. SVA questions. UPF questions. Short path algorithm between A and B Sorting array algorithm Give you basic design and ask you for verification plan, how will you implement scoreboard , why that choice... Question about blocking/non blocking assignment
Asked about clock domain crossing, asynchronous clocks, and difference between sequential and combinational logic.
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