Between timing and quality what would you prefer
Verification Interview Questions
3,655 verification interview questions shared by candidates
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UVM related, SV, RAL models etc Based on your resume - protocols
Tell me about a time... Describe a situation where...... How do you handle....
Explain my job experience and how relates to job applied for.
Explain a time you had to use better judgement when a manager wasn't around.
Q: Can you explain the difference between blocking and non-blocking assignments in SystemVerilog? Q: How would you verify a FIFO design? Q: What is a virtual interface and how do you use it in UVM? Q: How do you handle back-to-back transactions in a UVM sequence? Q: How do you debug a failing assertion in simulation?
Why do you want to work in health care?
what is mailbox why we don't use queue instead of mailbox. what is polymorphism and their uses. what is diff bw trsanction and transfer wrt axi.
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