Design a d latch using 2:1 MUX?
Verification Interview Questions
3,655 verification interview questions shared by candidates
What is the difference between latch and flipflop
Basic questions on digital like flip flop, latches ,verilog pattern detector code ,connection types,system verilog OOPs concepts ,arrays ,Basic questions on UVM like factory,common phases.
What is the Y model. Asked a bunch of questions on Digital Logic Design. 2 puzzles.
They asked About Projects initially and then core
Verilog Design based questions like: Difference between Mealy and Moore FSMs?
Which are the main differences between fork join, fork join_any and fork join_none?
Should be clear with basics in System Verilog and UVM to clear the technical rounds. Interviewer mainly focus on projects and ask to implement uvm testbench components and explain the process
Signed an NDA. Though, questions relevant to the role are asked.
Why I see myself in their company?
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