Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
Verification Interview Questions
3,654 verification interview questions shared by candidates
if I talk to your previous boss, what he/she/they gonna say about you?
model ADC in verilog, how to find frequency of a signal in verilog
Write the verilog code for D flip flop?
Write top level test bench that sets up he virtual interface
C++ question about returning the amount of bits in a certain value.
C++, SystemVerilog basics
how to impliment A=7.5B w/o using *, /
Some question related to accessing analysis ports in a sequence ( via sequencer)
Basic computer architecture questions, pipeline concepts and hazards. FSM for a sequence detector. Fibonacci using recursion and linked list reversal. Some scripting question which i could not answer.
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