C++ question about returning the amount of bits in a certain value.
Verification Interview Questions
3,654 verification interview questions shared by candidates
C++, SystemVerilog basics
if I talk to your previous boss, what he/she/they gonna say about you?
Some question related to accessing analysis ports in a sequence ( via sequencer)
Difference between verilog and sv.? Basic interface questions.
Asked about project details and uvm sv concepts
How will you verify this circuit ? ( A black box)
Previous project based questions Work Motivations Basic Engineering questions like Wireless technologies, SMPS, Power consumption etc
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
FSM for sequence detector. Verification environment. Verilog programming.
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