Constraint writing Assertion writing on given waveform
Verification Interview Questions
3,652 verification interview questions shared by candidates
As an ASIC verification Engineer Most of the questions were based on system Verilog and UVM. 1: Components of UVM, which components have you worked. 2: Phases in UVM 3: Assertions
Q: Tell me about your experiences
1.Introduction about yourself 2.Questions related to sv,uvm 3.Questions related to protocols 4.Coding skills
System verilog threads and Multiplexer and use of multiplexer.
What made you interested in this job?
Mainly about the projects with respect to both theoretical and technical knowledge. Along with it, some SV and UVM related questions like constraints, coverages, semaphore etc
Digital logic and C programming questions
They mostly concentrated on sv , uvm
A lot of technical questions relating to logic design, timing and IC design. Also a lot of questions about what I had worked on in the past.
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