Asynchronous FIFO full empty
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
ASIC Design
How would you go about verifying a design?
What was the name of the Colombus' ship?
We want to amplify a 100mV differential signal to 1V. How do you do this?
they asked me what I've been doing in my field. what class I liked most.
About digital,verilog,system verilog questions In sv oops concepts
DV team lead asked a question about mathematical proof for paired prime numbers characteristic.
1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
Describe the process for design of a new architecture and the refinement process
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