Fifo depth calculation 80/10 and 8/10.
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions.
blocking and non-blocking
Where do you see yourself in five years.
Psychological and Analytic questions would take a conscious presence of mind to go through, The question includes technical knowledge with twists
Basic c coding questions and digital electeonics questions
how to mimimize setup time and hold time violation?
4 bit counter
1. Verilog question: given 1 bit data, clock and 1 output. Every clock rise- the data is sampled. You need to turn on the output bit every time there is a sequence of 4 bits -1101.
What would be the effect of adding ESD protection to an output driver.
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