How to detect voltage source and current source in a black box
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
the difference between asic and fpga design
How do you combine states in a state machine. Do you actually save anything?
Could you replace the CPU cache with an SRAM? If you can what would be an advantage and disadvantage.
write a function of swap(a,b) in C/C++ using pass by reference and pass by value.
basic timing questions. I accepted the offer.3 rounds for contract position in VLSI Synthesis/STA all fundamentals are needed timing and synthesis prespective
how to generate a clock divide by 3
what is the 3 Cs in cache miss?
question on clock gating- for an 8-bit wide register ,what are the different ways in which clock gating can be implemented to reduce overall power
Which gate would you prefer in a design? Nand or Nor? why?
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