Design Questions and some logic questions
Asic Design Engineer Interview Questions
709 asic design engineer interview questions shared by candidates
Logical design, physical design, perl, System verilog (UVM)
Questions in digital design, timing violations, metastability
Moderate, no unexpected questions asked.
A hard Verilog question for a system.
Read after write sequence implementation
One hot encoding, FSM divide by 3, Verilog coding.
Design sequence detector with logic circuit diagram
Write the verilog of ROB on a paper.
Cache coherency, mapping techniques, metastability, cdc, synchronizers,
Viewing 651 - 660 interview questions