Could you please explain FIFO to me?
Asic Engineer Interview Questions
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Explain the UVM Sequencer driver communication
the journey and background till that moment.
Project on resume, CDC questions
Why do you want to join Synopsys?
Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
In the screening call: quetions about your background and personal projects, then 2/3 questions on digital design basics. Questions about Verilog HDL, logic synthesis, timing constraints, metastability, finite state machines, basics of verifications, testbenches, logic gates at transistor level, application of De Morgan law, small problem on digital circuits (counters, clock dividers, FSMs).
Clock Domain Crossing , RTL Design Constructs using Verilog , System Verilog and VHDL , Constraints in SDC, SDGC for spyglass
Pros and cons of vernier TDC
Digital questions, UVM environment based questions
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