UVM Verilog Verification thinking Logic gates
Asic Verification Engineer Interview Questions
230 asic verification engineer interview questions shared by candidates
Questions on constraints and assertions
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Explain about the AXI write process with signal descriptions
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Design a state machine to detect bit sequence. How do you verify it?
How to make nor gate using two input mux
There were no out of the box questions.
How to verify a fifo?
Your'e given a matrix MxN of 0's and 1's. everytime you encounter 1 cell, you need to put 0's in the rows and columns.
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