OOPS, SV, UVM and Cache
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
setup and hold time, flip-flop/latch design, how would you verify a design?
i have mentioned all the interview question above
Given a truth table, draw the corresponding diagram. I was also asked questions on level triggered/edge triggered (which one is safer...stuff like that). Code the solution in Verilog/VHDL.
Given a black box circuit and its truth table, use it to implement a NOT gate
Questions related to the work
How would you approach performance verification of a processor?
what is meant by Finite state machine?
What experiences do you have in the design process?
all about fifos nut and bolt details on languages, methodologies--felt a lot of emphasis on syntax too amidst continuous questions and conceptual explanations real life situations selected and you will be asked to analyze and provide the solution.
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