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Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
They asked about the design verification process, UVM concepts and coverage.
They mainly focused upon my resume and asked questions on projects
How does branch prediction work? What hardware mechanisms alleviate mis-predicts?
Draw the inverter's voltage transfer curve and explain what happens in each phase. Draw the cross section of a transistor and explain body effect.
Basic coding algorithm like sorting of arrays. PERL scripting basics.
How to verify the correctness of the design.
How to synchronize clocks between two systems
Setup Time, Hold Time, Max Clock Frequency and other usual Digital Design questions combined with a lot of difficult ones and some personality-based questions.
How can you write SystemVerilog constraints to generate a 5×5 matrix in which every element is unique within each row and unique within each column?
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