Find the bugs in Verilog code
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Series circuit analysis. (Going clockwise) there is a 1A current source followed by a 2 Ohm resistor followed by a 5V voltage source (negative pole connected to resistor). The current flows clockwise. What is the voltage across the current source?
Digital verilog systemverilog uvm fpga
What’s OOO how to design it Some design questions
Computer Architecture related. Explain different cache coherency protocol.
The interview with HR is simple, but interview with the director is technical! Questions depend on the exam.
Natural numbers Prime number Cube question cheppaga adhi Oka de question Randomisation use chesi oka game cheyyali Random ga generate Aina values ni nuvvu guess cheyyali test bench lo Avi match aithe pass Lekapothe fail 0,1,0,0,2,0,0,0,3.....
Uvm factory mechanism System verilog basics
there is nothign most difficult . if u dont know jst say "i dont know".
SV and UVM basics Logical questions
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