They asked about more on verilog coding, system verilog data types, uvm phases. Constraints, assertions and mathematical questions
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
What is the difference between a bipolar transistor and a mos transitor ?
Design the basic gates using 2:1 mux?
I have prepared to my interview
Tell me about uart protocol which I mentioned in resume
Aptitude and technical were asked
Basic verilog questions were asked including co-writing a program with an interviewer as well as from memory writing some functional blocks. Digital logic questions were also asked and used as a way to gauge how one might approach a larger-scale problem.
system verilog formats based on previous experience questons
What is handshake mechanism in uvm and explain how to override
what is 3`complement of 1010 ?
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