Explain about basic questions of digital electronics
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
1.diffrence between latch and flipflop. 2.explain delay and more 3.2x1mux using nand gates 4.write a verilog code for parity encoder. 5.write a verilog code and generate a clk for 100MHZ. 6.diffrence between display and write. 7.explain polymorphism. 8.explain TLM ports. 9.1010101010 genarate a sequence using constraints. 10.diffrence between dynamic array and associative array. 11. Explain and diffrence between case statement with syntax and ifelse statement
A complex circuit was given and I was asked to determine the critical path.
Write code for 3:8 Decoder using task?
how to verify a design
constraints: memory partition related constraints. assertions: implication and non implication
questions about Constraints, arrays, uvm sequences etc asked.
C++, Computer Architecture, Verilog and Academic Projects
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling, Arth overflow Stack over 1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?. 2. Also, How to write those test cases. ?
convert d flip flop to t flip flop
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