basics of digital electronics, verilog, sv,uvm
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Create a simple module in VHDL or Verilog, with some basic functionality
All the things that were mentioned in the resume.
First round some logical questions,FIFO depth related question. on 4 rounds, based on your experience , questions willl be on assertions, system veilog oops concepts,UVM TLM ports,FIFO in depth questions, But salary expectations will not be met.
- FIFO size requirement for write with same freq on write and read side for a burst size - A bunch of questions on polymorphism concept using parent and extended class handles and asking about the output - A bunch of questions around constraints in parent and extended class and asking what could be the values with the appropriate usage of polymorphism - A question on threads for fork join_any with delays and asking the sequence that would be seen on the output - Explain PCIe enumeration process - Explain Flow control process and the DL state machine handshake after Linkup happens
Describe virtual memory and the Memory Management Unit?
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Technical question in UVM, SystemVerilog, Digital Design
Sorting algorithm implementation, use adders to create a more complex circuit.
Low pass filter, inverting op amp output voltage, what is the high frequency part of a pwm signal. School courses
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