Verilog code for the clock divider Verilog code for clock generator for a particular frequency Same basic Verilog and System Verilog questions.
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Write UVM driver/monitor Come up with a test plan Write constraints
What are the performance tradeoffs of different cache architectures?
Coding the basic skeleton code for a given design. All UVM components should be coded and explained. This includes monitors, scoreboard logic, dut, agents , sequence items, sequence , driver and test
Questions on basic debugging skills using synopsys VCS. OOP concepts. Ethernet , AXI, APB protocols and their usage. Protocol bridge
Have you mentored anyone in your job? What did you learn and what would you do differently from that experience?
It consisted of 2 rounds. In Round 1 they asked about basics of digital electronics, cro, osciloscope. In Round 2, they asked to code traffic light controller o verilog and discuss its area, power
Questions based on digital are from FSM and flip flops, From verilog there are questions based on always initial block, blocking and non blocking assignments, and data types From Systemverilog there are questions from data types, array, OOPS concept
priority encoder MUX conversions array manipulation
design FSM given a sequence
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