: first given a block which you can see its interface and what would you check in order to make sure that the component works as it should the component was something like a memory. second question is a simple leet code question.
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
How will you deal with a difficult design engineer?
Verilog Design and verification related
Teamwork that related to the position.
UVM concepts, assertions, tb arch
What's pipelining? What's cache coherency?
My previous experience, basic assertions and fifo programming
Lcm, Swap, Factorial for C coding Write constraints in system verilog
What products of the company do you know? tell me a project you have done in the past and what did you learn form it..what would you change.. write 2 little projects in VHDL or Verilog (a state machine and a counter).. explain what you did..
Some basic questions/tasks about C programming (pointers, arrays..), design task for receiving data bytes from the transmitter (C programming), Asked to explain different parts of some old SOC configuration. For people studying only Electronics I would suggest going through Software Engineering lectures from other courses to know about how memory is managed in a SOC and CPU. Ideally read about the Architecture of CPU and Microcontrollers as I was asked this in all 3 Interviews with ARM. I only studied Electronics and had no courses related to this except when we briefly looked into simple microcontrollers without going into detail so it was good decision going through Software Engineering course notes before the interview.
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