Questions on GATE level questions all digital electronics
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Design an 1×4 demux using 2×1mux
About projects and Static timing analysis
No one show up for the interview
nand gate using 2x1 mux
Why do we use virtual sequence. Virtual interface.
The first thing was a phone call with the recruiter where he asked questions like my interests, past experience, graduation date, etc. In the coding round 1: SystemVerilog FSM question + behavioral Then the coding round 2: Python question + behavioral
What does functional coverage is 70% and code coverage 100% means?
asked to draw half adder .number conversions were asked
what would happen in the following case? class my_class ; endclass my_class my_object; my_class array[N:1]; my_object=new (); for (i=0;i<N;i++) array[i] = my_object;
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