How do I reduce power at the system level?
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
design mod 4 counter using T flipflop design a fulladder using logic gates
Design a mod 5 counter
1. What is actually happen from moving the mouse physically to the the cursor moves? 2. Follow up the question 1, asking you to explain some OS questions, like what is interrupt.
Basics of digital, verilog, system verilog and uvm.
Given a function in C++, describe the intended purpose, what it returns, and fix the code so it actually returns what it is meant to return.
Given this design and their features, explain how you would build a UVM testbench to verify it.
Design a full adder using MUX
What is a state machine?
A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
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