Constraint and assertion , gate level simulation
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Questions on interface, clocking blocks, assertions, uvm, X propagation.
Asked me to tell about myself, past work I’ve done, what do I expect from my new team, manager, etc.
Dont remember much but mostly code deep dives and situational questions related to work.
Draw the circuit base on the coding provided
Power of 2, asynchronized and synchronized reset
1. C++, OOP 2. python: dictionary, swap values 3. Systemverilog: fork join 4. delete repeated element in an array 5. FIFO depth 6. find SA0/SA1 amoung 128 wires in minimal steps
Given an array of N elements and an array of M elements, both sorted in ascending order, create an array C that combines A and B in ascending order.
Can you talk about your past experiences?
Functional coverage vs. Code Coverage
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