Questions on C++, Perl, System Verilog.
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
Explain about FIFO, Clk generation, State machine
Verilog based questions - circuit was given and then i had to give an optimized code for it.
every details on uvm, some coding question and data structure
Tell me about yourself. Do you mind to relocate?
The asked about past work experience.
What is your experience with random constrained stimulus?
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
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