Difference between task and function.
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
1. on bits and bytes 2. virtual class output questions were there 3.
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
The questions in the first interview were mostly about C semantics and rules. Nothing fancy, but you should know the nuances of the language.
Waiting for interview to be held. Will update once done
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Q1: verification plan for a stated scenario
1. Some simple random stimulus with specified constraints
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