OOP and polymorphism. Basic System Verilog and UVM coding.
Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Convert the RTL logic to a gatelvel netlist. Constraint question from system verilog.
1. constraints 2. assertions 3. UVM topology
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
Parler nous de vos experiences.
masters project in in depth in terms of technicalities
About digital electronics for VLSI domain
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
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