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Design Verification Engineer Interview Questions
950 design verification engineer interview questions shared by candidates
Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
Find the number of '5''s in a rolling window of size 10. Flag an error when the count>4
My experience was bad in 2 rounds otherwise good in other 3 rounds.
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
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Given read and write freq, how to calculate FIFO depth?
questions about OVM process
How to convert hexadecimal to decimal.
- about SV, FIFO design, arbiter design
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