Design Verification Interview Questions

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Make an AND gate from a 2-to-1 mux and make a k-map for that set-up, write code (any language) to arrange a N-sized list of numbers in ascending or descending order, what is set time, hold time, and metastability, divide a clock signal by three
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Design Verification Intern

Interviewed at Texas Instruments

3.8
Nov 10, 2024

Make an AND gate from a 2-to-1 mux and make a k-map for that set-up, write code (any language) to arrange a N-sized list of numbers in ascending or descending order, what is set time, hold time, and metastability, divide a clock signal by three

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