Synchronous FIFO (based on the project), Memory design, C programming questions
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
2 rounds of Interview happened on the same day on call. Asked to code the monitor for a DUT. DUT was loaded with all the conditions with how it works which made it complex. SV constraint and some algorithm related questions were asked. All were of good quality.
static timing analysis
network theory
Define verilog ,systemverilog. Memory /cache
The first round had questions based on signal processing, basics of system Verilog, and I was given a take-home coding task to write an RTL code to check if there is an increment, decrement by 1 bit and if not, print error; and verify the same using a class-based testbench.
C++, SystemVerilog basics
if I talk to your previous boss, what he/she/they gonna say about you?
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
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