Cache Coherency, UVM and TLM related, SV concepts, Past projects.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Memory Consistency
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
setup/hold time ;verification coverages and types
Q1. FIFO depth, given read and write rates for a burst of x writes Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms) Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms) Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms) Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms) Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
How to implement a priority encoder in Verilog?
Describes one of your projects
FSM, SystermVerilog, and software leetcode related questions.
Q. Describe your test plan for a FIFO
write HDL code for a FSM
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