1. What are the pros and cons of adding an extra stage in a CPU 2. Follow-up: How does adding a stage affect the setup time and hold time
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Computer Architecture, Coding in SystemVerilog
write HDL code for a FSM
FSM, SystermVerilog, and software leetcode related questions.
Explain encapsulation, inheritance, polymorphism. How does a TLB work and why is it necessary?
What's your name , is it [name] ?
implementation of driver class based on the figure they gave
FIFO implementation Coding problem Asked about project i did
UVM based questions and Assertions and constraints
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
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