All the concepts of STA
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
What is pd flow and explain them with their input and outputs
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
scripting, low power in vlsi, general digital vlsi question, depth questions in PnR flow
AOCV and POCV in detail
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
Phone screening 1. Questions about previous work experiences, digital circuit/layout design. 1:1 Technical interviews 1. RC circuits. Response to step input signal. 2. Transistor sizing for better setup/hold times. 3. Layout design of NAND3/NOR3 gates in different styles 4. Elmore delay of complex gates. 5. Standard cell library architecture choices and tradeoffs 6. Physical verification of standard cell libraries 7. DFM/DFD questions 8. Perl/Tcl and EDA tool related questions
Most questions were based on STA, timing and some based on PERL.
Explain Semi custom flow. STA. Layout verification related.
Basic pd questions, logical thinking
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