Walk me through how you approach floorplanning for a block. How do you handle placement of macros and standard cells around them? What considerations go into designing a power grid? How do you handle multi-VDD domains or level shifters? What are tie-high and tie-low cells and where are they used?
what are different PV checks?
Explain ASIC Design Flow? Explain about Placement congestion and how to reduce it? Write a TCL script for searching a slack value which is violated in a report and write those values in another file?
setup. hold. optimizations. transistor level questions. timing circuits
voltages across capacitors and resistors mix circuits
What is negative slack Does setup and hold occur in a single cycle Briefly explain place and route flow How to you efficiently build the clock tree
modulo 3 and xor in wave form
The question was about the placement of flops during routing. The interviewer asked me if there is a wire or an interconnect where exactly would I want to place a flip flop into the design-At the start, in the middle or the end. She gave X, Y locations and wanted me to identify where I would be placing the flops to stabilize the design.
Nothing unexpected they ask only valid questions at least which are required for them
PNR flow and basics of PD
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