Area of the design in my past project. Best design practices. Antenna effects.
Soc Design Engineer Interview Questions
100 soc design engineer interview questions shared by candidates
Pseudo code for MUX Setup and hold time
Program to differentiate even and odd number Draw and explain NOT and NAND gate Draw a stick diagram for NOT gate Find ways to make NAND gate a NOT gate Explain methods of verifying your design, such as DFT Scan path.
been too long dont remember any questions
What are Setup Time and Hold time violations and how to fix them?
Resume shortlist were there Digital design questions were there Sta questions were there Verilog questions were there Computer architecture questions were there Device physics questions were there Some puzzles were there Hr questions were there
1) C++ code to set the matrix MxN to zero if any element in MxN is zero. (leetcode medium question) 2) write constraint to set 32 bit address to be word aligned and 1kb in length
Hold and setup time, FSMs
What was the major challenge you faced while working on this project?
STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?
Viewing 91 - 100 interview questions
See Interview Questions for Similar Jobs
Soc Physical Design EngineerAsic EngineerVlsi EngineerHardware Asic Design EngineerAsic Design Verification EngineerAsic Physical Design EngineerVlsi Design EngineerElectrical Hdwr Engineer IFpga Design EngineerAsic Design EngineerFirmware EngineerAsic Verification EngineerVlsi Cad Tool Support EngineerPhysical Design EngineerCpu Design EngineerFpga Hardware Design EngineerFpga EngineerSenior Vlsi Design Engineer