CDC- slow to fast, fast to slow crossing. Sycn FIFO and ASycn FIFO - Differences
Soc Design Engineer Interview Questions
100 soc design engineer interview questions shared by candidates
basics of cmos inverter, digital circuits, verilog, RTL to GDSll flow.
UVM Concepts and Work Experience of previous project
LRU policy, programming, state machine encoding
Pick a recent project to present
Prepare well for the interview
Basic Verilog questions, FSM, Synchronizers, Clock Domain Crossing, Sequence detectors, Clock divider circuits, FIFO, Async FIFO, Circuit to detect the number of 1's using adders and then using only combinational logic, Transpose a Matrix using C. I was asked to code on almost all of the topics mentioned above.
Some system verilog Questions
Basically covered VLSI basics, ASIC flow basics (each step) and scripting. Friendly chat for behavioral interview.
CMOS inverter questions. Power related questions
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