There were 4 rounds - 3 technical and 1 HR.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
what is blocking and non blocking?
On projects and sv uvm based Protocol knowledge on what we mentioned in resume
mostly in uvm and sv
Constraint and assertion , gate level simulation
Questions on interface, clocking blocks, assertions, uvm, X propagation.
Explain about FIFO, Clk generation, State machine
Verilog based questions - circuit was given and then i had to give an optimized code for it.
every details on uvm, some coding question and data structure
Tell me about yourself. Do you mind to relocate?
Viewing 591 - 600 interview questions
See Interview Questions for Similar Jobs
Fpga Design EngineerVerification EngineerRtl Design EngineerVlsi Design EngineerLogic Design EngineerPhysical Design EngineerCpu Design EngineerElectrical Product Design EngineerSenior Vlsi Design EngineerSenior Fpga Design EngineerVerification ManagerSenior Asic Fpga Design EngineerApplication Design EngineerHardware Design EngineerSenior Physical Design EngineerIc Design EngineerFpga Development EngineerAsic Verification Engineer