Asked me to tell about myself, past work I’ve done, what do I expect from my new team, manager, etc.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Questions on interface, clocking blocks, assertions, uvm, X propagation.
Dont remember much but mostly code deep dives and situational questions related to work.
I was asked to write system verilog constraints for a variety of random stimulus needs.
What is the difference between blocking and non-blocking assignments?
1. C++, OOP 2. python: dictionary, swap values 3. Systemverilog: fork join 4. delete repeated element in an array 5. FIFO depth 6. find SA0/SA1 amoung 128 wires in minimal steps
Questions on C++, Perl, System Verilog.
Can you talk about your past experiences?
Functional coverage vs. Code Coverage
What is an Agent? Passive vs. Active.
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