Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Questions on protocols like API, AXI, AHB, API, UART.
Basics of Digital Electronics and Verilog
2 lists which are connected. find the joint element
2 rounds of Interview happened on the same day on call. Asked to code the monitor for a DUT. DUT was loaded with all the conditions with how it works which made it complex. SV constraint and some algorithm related questions were asked. All were of good quality.
static timing analysis
network theory
Define verilog ,systemverilog. Memory /cache
DSP, OOPs Concepts, Basics CMOS based concepts
What is the difference between SV function and Verilog function?
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