Uvm phasing process, different phases in uvm
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
What will you do if you made a big mistake?
write code which returns error if we got 10 packets within 10 seconds
DSP, OOPs Concepts, Basics CMOS based concepts
What is the difference between SV function and Verilog function?
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
C++, SystemVerilog basics
if I talk to your previous boss, what he/she/they gonna say about you?
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
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