How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
System Verilog Virtual functions
System Verilog ,UVM Basics, Questions on Resume. Assertions,Constraints. Memory Verification plan
Constraint randomization based question linking to AXI and memory filling
Confidential. But related to system verilog and uvm.
design a vending machine from architecture to rtl..
Describe your previous projects and describe your contribution in them
bitmasking using systemverilog C++ classes
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
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