Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Find the number of '5''s in a rolling window of size 10. Flag an error when the count>4
My experience was bad in 2 rounds otherwise good in other 3 rounds.
I was given a direct coding question about how I would determine whether two patterns given to me were correct.
implement blackjack with classes in python
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
Given read and write freq, how to calculate FIFO depth?
questions about OVM process
Write code for a UVC mimicing a memory . Reactive sequence in UVM
Viewing 931 - 940 interview questions
See Interview Questions for Similar Jobs
Fpga Design EngineerVerification EngineerRtl Design EngineerVlsi Design EngineerLogic Design EngineerPhysical Design EngineerCpu Design EngineerElectrical Product Design EngineerSenior Vlsi Design EngineerSenior Fpga Design EngineerVerification ManagerSenior Asic Fpga Design EngineerApplication Design EngineerHardware Design EngineerSenior Physical Design EngineerIc Design EngineerFpga Development EngineerAsic Verification Engineer