Describe Yourself, project related question.
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
1. Basics of system verilog and uvm ll be asked, 2. description of project worked on 3. Bugs found and issuedls faced
Basic SV, UVM, Verilog, Verification flow etch
Testing methodologies and Test case scenarios
1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors
FIFO, LIFO in Verilog
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
Where do you see yourself in 5 years?
Why should i be hiered?
Algorithm from a published article and explain what this algorithm do.
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