System verilog,uvm,verilog constraints and assertions , about projects
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Lcm, Swap, Factorial for C coding Write constraints in system verilog
How to have accurate testing when you a large test case to cover.
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Questions on C# basics like hex code of 17, what is Class and Method. Asked to fill the empty spaces oin written C# code. Questions asked on Siemens PLC programming.
- code coverage: types, why, how to collect, analysis. Functional coverage: why, how, analysis.
- structure of a typical verification environment, explain each block. Verification closure process. Top/chip level verification, block level reuse techniques.
- problem solving: 1) write systemverilog properties to verify a given, simple protocol. 2) compute the optimal FIFO depth given the in and out timing specs. 3) Write the RTL for a FSM then synthesize it.
Mostly about verilog, Problem solving skills
Verilog based basic questions , SV and UVM questions
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