Define verilog ,systemverilog. Memory /cache
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
no really difficult questions
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
First round: 1) Introduction on your experience, the job profile requirement and your motivation. DIscussion our application and CV. Second Round: 1) Technical questions on the projects you worked on. This will be in details. Both simulation based ( SV/UVM) and formal methods were discussed. Third round (HR): 1) very generic HR questions like, tell me about your self, your strengths/weakness, motivation to join Synopsys, what your team will say about you . describe a conflicting situation you handled, how do you keep your team motivated, salary expectations and personal situation etc.
1. Describe verification process of some modules 2. Describe typical test environment (monitor, driver etc) 3. Some common SystemVerilog problems and questions
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
where do you see yourself in 5 years
What will you do if you made a big mistake?
- How yours skills will fit the position? - A behavioral question about how would you behave if you have opposite opinions with your manager
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