write code which returns error if we got 10 packets within 10 seconds
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
They asked me 1)about the various concepts of verifying a design and also provided me scenarios as to how we can verify them . 2)to explain my previous projects and my responsibilities for each of the projects . 3)Also, the software team asked me a programming example. There were various teams of people wanting me to explain my previous job profile and responsibilities and explaining me about their company culture. Overall, It was a very good experience for me since I was fascinated by the fact that my job profile and trading can coincide !! and how!
DSP, OOPs Concepts, Basics CMOS based concepts
What is the difference between SV function and Verilog function?
Can you tell me your years of experience in ____ ?
verify a FIFO using formal verification techniques and methods to resolve complexity
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
FPGA Verification engineers need SystemVerilog and UVM experience
design and verify a module
Can’t remember much but some fcov syntax related questions
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