Confidential. But related to system verilog and uvm.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
How many times does the clock hands cross each other throughout the day?
remove duplicates from array in place
Describe your previous projects and describe your contribution in them
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
Create an FSM for detecting a sequence
My previous experience, as well as a few mock examples related to verification and what my process would be
more on application oriented uvm config_db and resource_db register bits swapping verification fifo based questions
The other 3 questions had design scenarios where I had to plan testcases to check their correctness...
Questions related to a verilog project I did in college.
Viewing 1981 - 1990 interview questions