question around the system verilog ,verification methodology.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
OOPs questions and also ASIC and Verfication based questions
what do u know about virtual pages
3. A linked list that is one-directed, how can you tell there is a loop without using another data set? You can write it in pseudo-code
each interview had at least 3 RTL design questions
Give a detailed example of a test you wrote
bitmasking using systemverilog C++ classes
Four people need to cross a rickety bridge at night. Unfortunately, they have one torch and the bridge is to dangerous to cross without a torch. The bridge can support only two people at a time. All the people don’t take the same time to cross the bridge. Time for each person: 1 min, 2 mins, 7 mins, and 10 mins. What is the shortest time needed for all four of them to cross the bridge?
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