System Verilog Virtual functions
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
System Verilog ,UVM Basics, Questions on Resume. Assertions,Constraints. Memory Verification plan
Basic UVM questions, monitor code and writing constraints.
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is the difference between Mealy and Moore machines?
where do you see yourself in 5 years
What will you do if you made a big mistake?
- How yours skills will fit the position? - A behavioral question about how would you behave if you have opposite opinions with your manager
verify a FIFO using formal verification techniques and methods to resolve complexity
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
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