What is the difference of function and task in verilog
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What's your name , is it [name] ?
Tell us more about your experience
Computer Architecture, Coding in SystemVerilog
UVM, components, monitor, driver, constraints
Design an FSM for a 2-clock system
Computer architecture, some verification questions
What is gray code and 8b10b encoding, and why they are useful
Q. What are all run-phases and in detail discussion about it Q. Basic constraints related to dist, and assertion
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